High-capacitance capacitors such as finger metal oxide metal (FMOM) capacitors are widely used in various types of analog and digital circuits such as phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs), etc. Generally, such a capacitor has two sets of parallel conductive lines or fingers. Each set of fingers may be connected to a terminal of the capacitor. The capacitance of an FMOM capacitor depends on the number of conductive lines that are connected to a voltage terminal, and their respective length, width, and distance to neighboring conductive lines that are connected to another voltage terminal.
In general, two or more sub-capacitors may be stacked on a semiconductor substrate to form a high-density capacitor structure with high capacitance. However, such a capacitor structure may also increase the parasitic capacitance in the capacitor structure due to fabrication constraints (e.g., metal density rules). Parasitic capacitance (also referred to as stray capacitance or self-capacitance) is one of the physical constraints that limits the performance of integrated circuits. Parasitic capacitance may exist within parts of an integrated circuit or component due to their proximity to each other. As such, the presence of parasitic capacitance may further increase capacitive coupling between adjacent metal layers in the capacitor structure and this may interfere with normal circuit operations.
Additionally, the presence of parasitic capacitance may create variations in capacitance from the capacitor structure to unwanted stray capacitance effects (e.g., noise, cross talks). For example, one terminal of the capacitor structure that charges and discharges current may create parasitic capacitance imbalance with the other terminal of the capacitor structure. The variation in parasitic capacitance between terminals in the capacitor structure may cause the linearity of the integrated circuit to be affected, which in turn may degrade circuit performance.